Physical Design Engineer Layout Engineer m/f


Physical Design Engineer Layout Engineer m/f

Job Description

Creates bottoms-up elements of chip design including but not limited to FET, cell, and block-level custom layouts, abstract view generation, RC extraction and schematic-to-layout verification and debug using phases of physical design development including parasitic extraction, polygon editing, auto-place and route algorithms, floor planning, full-chip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments.


Qualifications

Qualifications:- FH/University degree in electronics - Knowledge in analog layout and design - Knowledge in Cadence Design Framework and Calibre is welcome but not required- Knowledge in UNIX/Linux operating systems is welcome but not required - Languages: English and German


Inside this Business Group

Intel is a leading provider for technologies that support wireless and handheld computing devices. The Wireless Communications and Computing group develops essential technologies, architectures and building blocks to support advanced processing, communications and memory aspects of both personal digital assistants (PDAs) and wireless handsets.
Stelleninformation
Inserent Intel - Germany
Kontaktname
Telefon (Beziehen Sie sich auf Dice)
Referenz JR0043740

Copyright © 2017, Dice

Dice ist ein DHI Service

            
                                                                        

          

                       

search